DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 634

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI)
14.7.2
Figure 14.22 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
Rev. 2.00 Jun. 28, 2007 Page 608 of 864
REJ09B0341-0200
is secured as a guard time after the end of the parity bit before the start of the next frame.
has passed from the start bit.
after at least 2 etu.
In normal transmission/reception
When a parity error is generated
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Data Format (Except in Block Transfer Mode)
Figure 14.22 Data Formats in Normal Smart Card Interface Mode
(Z)
Ds
Ds
Start bit
Parity bit
Error signal
Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0)
Ds
A
D0
D0
D0
Z
D1
D1
D1
Z
Output from the transmitting station
Output from the transmitting station
D2
D2
D2
A
D3
D3
D3
Z
D4
Z
D4
D4
D5
Z
D5
D5
D6
A
D6
D6
D7
A
Dp
D7
D7
Z
Dp
Dp
(Z) state
Output from
the receiving station
DE