DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 111

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.7
There are three instructions that cause exception handling: trap instruction, sleep instruction, and
illegal instruction.
4.7.1
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state. The trap
instruction exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
A start address is read from the vector table corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling.
Table 4.8
[Legend]
1:
0:
:
Interrupt Control Mode
0
2
the TRAPA instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
Set to 1
Cleared to 0
Retains the previous value.
Instruction Exception Handling
Trap Instruction
Status of CCR and EXR after Trap Instruction Exception Handling
I
1
1
CCR
UI
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
Rev. 2.00 Jun. 28, 2007 Page 85 of 864
T
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0
Section 4 Exception Handling
EXR
REJ09B0341-0200
I2 to I0
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