DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 661

IC H8SX/1657 MCU FLASH 120TQFP

DF61657CN35FTV

Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61657CN35FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
DF61657CN35FTV
Manufacturer:
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Part Number:
DF61657CN35FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 15.4 shows the A/D conversion timing. Table 15.3 indicates
the A/D conversion time.
As indicated in figure 15.4, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 15.3.
In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in
table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
SPL
). The length of t
Input Sampling and A/D Conversion Time
D
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
(2):
t
t
t
D:
SPL
CONV
varies depending on the timing of the write access to ADCSR. The total
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 15.4 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) passes after the ADST bit in ADCSR is set to
t
CONV
CONV
) includes t
Rev. 2.00 Jun. 28, 2007 Page 635 of 864
D
and the input sampling time
Section 15 A/D Converter
REJ09B0341-0200

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