DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 147

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When the same interrupt source is set as both the DTC and DMAC activation source and CPU
interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in
CPUPCR is set to 1, the priority is determined according to the IPR setting corresponding to the
interrupt source. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt
source must be set to lower than or equal to the DTCP and DMAP setting. If the CPU is given
priority over the DTC and DMAC, the DTC and DMAC may not be activated, and the data
transfer may not be performed.
(2)
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 8.1, in section
8.4, Location of Transfer Information and DTC Vector Table.
(3)
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC or DMAC activation source or CPU interrupt source, respective operations
are performed independently.
Table 5.6 lists the selection of interrupt sources and interrupt source clear control by setting the
DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the
DISEL bit in MRB of the DTC.
Table 5.6
[Legend]
√:
O:
X:
*:
DMAC Setting
DTA
0
1
The corresponding interrupt is used. The interrupt source is cleared.
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
The corresponding interrupt is used. The interrupt source is not cleared.
The corresponding interrupt is not available.
Don't care.
Priority Determination
Operation Order
Interrupt Source Selection and Clear Control
DTCE
0
1
*
DTC Setting
CISEL
*
0
1
*
DMAC
O
O
O
√
Interrupt Source Selection/Clear Control
Rev. 2.00 Jun. 28, 2007 Page 121 of 864
DTC
X
√
O
X
Section 5 Interrupt Controller
REJ09B0341-0200
CPU
√
X
√
X