DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 471

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4
10.4.1
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
(1)
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
(a)
Figure 10.2 shows an example of the count operation setting procedure.
Select output compare register
Select counter clearing source
Counter Operation
Example of count operation setting procedure
Select counter clock
Operation selection
<Periodic counter>
Periodic counter
Start count
Operation
Basic Functions
Set period
Figure 10.2 Example of Counter Operation Setting Procedure
[1]
[2]
[3]
[4]
[5]
<Free-running counter>
Free-running counter
Start count
[5]
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jun. 28, 2007 Page 445 of 864
[1]
[2]
[3]
[4]
[5]
Select the counter clock with bits TPSC2
to TPSC0 in TCR. At the same time,
select the input clock edge with bits
CKEG1 and CKEG0 in TCR.
For periodic counter operation, select the
TGR to be used as the TCNT clearing
source with bits CCLR2 to CCLR0 in
TCR.
Designate the TGR selected in [2] as an
output compare register by means of
TIOR.
Set the periodic counter cycle in the TGR
selected in [2].
Set the CST bit in TSTR to 1 to start the
counter operation.
REJ09B0341-0200