DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 201

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.6
The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications
can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDINCR.
6.6.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space,. For details, see section 6.5.6, Endian and Data Alignment.
6.6.2
Table 6.15 shows the pins used for basic bus interface.
Table 6.15 I/O Pins for Basic Bus Interface
Note:
Name
Bus cycle start
Address strobe
Read strobe
Read/write
Low-high write
Low-low write
Chip select 0 to 7
Wait
*
Basic Bus Interface
Data Bus
I/O Pins Used for Basic Bus Interface
When the address/data multiplexed I/O is selected, this pin only functions as the AH
output and does not function as the AS output.
Symbol
BS
AS*
RD
RD/WR
LHWR
LLWR
CS0 to CS7 Output
WAIT
I/O
Output
Output
Output
Output
Output
Output
Input
Strobe signal indicating that an address output on the
address bus is valid during access
Strobe signal indicating the read access
Signal indicating the data bus input or output
direction
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Strobe signal indicating that the area is selected
Wait request signal used when an external address
space is accessed
Function
Signal indicating that the bus cycle has started
Rev. 2.00 Jun. 28, 2007 Page 175 of 864
Section 6 Bus Controller (BSC)
REJ09B0341-0200