DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 680

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.7
20.7.1
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR_1
PSS = 1.
In watch mode, the CPU is stopped and peripheral modules other than RTC are also stopped. The
contents of the CPU’s internal registers, the data in internal RAM, and the statuses of the internal
peripheral modules (excluding the A/D converter) and I/O ports are retained. To make a transition
to watch mode, bits SCK2 to SCK0 in SCKCR must be set to 0.
20.7.2
Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0, to IRQ7), or signals at
the RES, MRES*, or STBY pin.
• Exiting Watch Mode by Interrupts
• Exiting Watch Mode by RES or MRES* pin
• Exiting Watch Mode by STBY pin
Note:
Rev.7.00 Dec. 24, 2008 Page 624 of 698
REJ09B0074-0700
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON
bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI
circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0
has elapsed. In case of IRQ0, to IRQ7 interrupts, no transition is made from watch mode if the
corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case of
interrupts from the internal peripheral modules, the interrupt enable register has been set to
disable the reception of that interrupt, or is masked by the CPU.
See section 20.4.3, Setting Oscillation Stablization Time after Clearing Software Standby
Mode, for how to set the oscillation settling time when making a transition from watch mode to
high-speed mode.
For exiting watch mode by the RES or MRES* pin, see section 20.4.2, Clearing Software
Standby Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
* Supported only by the H8S/2218 Group.
Watch Mode
Transition to Watch Mode
Exiting Watch Mode