DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 186

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
Only the basic bus interface can be used for the area 7.
6.4.4
In the H8S/2218 Group chip select signals (CS0 to CS5) can be output to areas 0 to 5, the signal
being driven low when the corresponding external space area is accessed. Figure 6.3 shows an
example of CSn (n = 0 to 5) output timing. Enabling or disabling of the CSn signal is performed
by setting the data direction register (DDR) for the port corresponding to the particular CSn pin.
In ROM-disabled extended mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS5 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS5.
In ROM-enabled extended mode, pins CS0 to CS5 are all placed in the input state after a power-on
reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS5. For
details, see section 8, I/O Ports.
Rev.7.00 Dec. 24, 2008 Page 130 of 698
REJ09B0074-0700
Chip Select Signals
Address bus
Figure 6.3 CSn Signal Output Timing (n = 0 to 5)
φ
CSn
T
1
Area n external address
Bus cycle
T
2
T
3