DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 569

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Universal Serial Bus (USB)
14.5.6
Bulk-In Transfer (Dual FIFOs) (Endpoint 1)
EP1 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write should be performed for one
FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP1PKTE at one
time after consecutively writing 128 bytes of data. EP1PKTE must be performed for each 64- byte
write.
When transmitting data to the host by bulk-in transfer, first enable the EP1 FIFO empty interrupt
by writing 1 to EP1EMPTYE in UIER1. At first, both EP1 FIFOs are empty, and so an EP1 FIFO
empty interrupt is generated immediately. The data to be transmitted is written to the data register
using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and
so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full,
EP1EMPTY is cleared to 0. If at least one FIFO is empty, UIFR1/EP1EMPTY is set to 1. When
ACK is returned from the host after data transmission is completed, the FIFO used in the data
transmission becomes empty. If the other FIFO contains valid transmit data at this time,
transmission can be continued.
When transmission of all data has been completed, write 0 to UIER1/EP1EMPTYE and disable
EXIRQ0 or EXIRQ1 interrupt requests.
Rev.7.00 Dec. 24, 2008 Page 513 of 698
REJ09B0074-0700