DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 427

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
Bit Name Initial Value
GM
BLK
0
0
R/W
R/W
R/W
Description
GSM Mode
Setting this bit to 1 allows GSM mode operation. In GSM
mode, the TEND set timing is put forward to 11.0 etu
from the start and the clock output control function is
appended. For details, see section 12.7.9, Clock Output
Control.
0: Normal smart card interface mode operation
(1) The TEND flag is generated 12.5 etu (11.5 etu in the
(2) Clock output on/off control only.
1: GSM mode operation in smart card interface mode
(1) The TEND flag is generated 11.0 etu after the
(2) In addition to clock output on/off control, high/how
Setting this bit to 1 allows block transfer mode operation.
For details, see section 12.7.4, Block Transfer Mode.
0: Normal smart card interface mode operation
(1) Error signal transmission, detection, and automatic
(2) The TXI interrupt is generated by the TEND flag.
(3) The TEND flag is set 12.5 etu (11.0 etu in the GSM
1: Operation in block transfer mode
(1) Error signal transmission, detection, and automatic
(2) The TXI interrupt is generated by the TDRE flag.
(3) The TEND flag is set 11.5 etu (11.0 etu in the GSM
(initial value)
(initial value)
block transfer mode) after the beginning of the start
bit.
beginning of the start bit.
fixed control is supported (set using SCR).
data retransmission are performed.
mode) after transmission starts.
data retransmission are not performed.
mode) after transmission starts.
Rev.7.00 Dec. 24, 2008 Page 371 of 698
REJ09B0074-0700

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