DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 159

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
5.6.1
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Interrupt
Control Mode
0
2
request is sent to the interrupt controller.
pending. If the I bit is cleared, an interrupt request is accepted.
the priority system is accepted, and other interrupt requests are held pending.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority Setting
Register
Default
IPR
Interrupt Mask
Bits
I
I2 to I0
Description
The priority of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is marked by
the I bit.
8-level interrupt mask control is performed by
bits I2 to I0.
8 priority levels other than NMI can be set with
IPR.
Rev.7.00 Dec. 24, 2008 Page 103 of 698
REJ09B0074-0700