DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 492

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
16. Notes on Wait Operation in Master Mode
Rev. 5.00 Sep. 01, 2009 Page 440 of 656
REJ09B0071-0500
(Master transmit mode)
(Master transmit mode)
(Slave receive mode)
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to
1 according to the order below.
(1) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
(2) Set the MST bit to 1.
(3) To confirm that the bus was not entered to the busy state while the MST bit is being set,
When attempting to use the wait function in master mode, if the interrupt flag IRIC bit is
cleared from 1 to 0 between the falling edges of the seventh and eighth clock pulses, the LSI
may fail to enter wait status after the falling edge of the eighth clock pulse and instead output
the ninth clock pulse continuously.
When using the wait function, keep the following points in mind with regard to clearing the
IRIC flag.
Ensure that the IRIC flag is set to 1 at the rising edge of the ninth clock pulse and cleared to 0
before the rising edge of the seventh clock pulse (when the counter value in BC2 to BC0 is 2
or higher).
I
I
2
2
C bus interface
C bus interface
Other device
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Figure 14.27 Diagram of Erroneous Operation when Arbitration Is Lost
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
A
A
A
2
C protocol, the same problem may occur when the MST
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as an
• When the receive data matches to
receive mode
address
the address set in the SAR or SARX
register, the I
as a slave device.
SLA
DATA1
DATA2
2
C bus interface operates
Transmit data does not match
R/W
A
A
DATA4
DATA3
Data contention
A
A