DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 186

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.5.7
Table 8.6 lists execution status for a single DTC data transfer, and table 8.7 shows the number of
states required for each execution status.
Table 8.6
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 8.7
Legend:
m: The number of wait states for accessing external devices.
Note: * Cannot be used in this LSI.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Rev. 5.00 Sep. 01, 2009 Page 134 of 656
REJ09B0071-0500
Mode
Normal
Repeat
Block transfer
Bus width
Access states
Execution
Status
Object to be Accessed
Number of DTC Execution States
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
S
S
S
S
S
S
I
J
K
K
L
L
M
Register
Information
Read/Write
J
6
6
6
Chip
RAM
On-
32
⎯
1
1
1
1
1
1
ROM
Chip
On-
16
⎯
1
1
1
1
1
1
Data Read
K
1
1
N
Internal I/O
Registers
⎯
⎯
8
2
2
4
2
4
16
⎯
⎯
2
2
2
2
2
1
Data Write
L
1
1
N
⎯
2
4
2
4
2
4
External Devices *
8
6 + 2 m
6 + 2 m
6 + 2 m
3 + m
3 + m
⎯
3
Internal
Operations
M
3
3
3
⎯
2
2
2
2
2
2
16
3 + m
3 + m
3 + m
3 + m
3 + m
⎯
3