DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 435

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

IICIC05B_000020020700
An I
when using this option.
• For mask-ROM versions, a W is added to the part number in products in which this optional
The H8S/2268 Group has an internal I
has that of one channel.
The I
interface functions. The register configuration that controls the I
Philips configuration, however.
The I
each channel, which allows efficient use of connectors and the area of the PCB.
14.1
• Selection of I
I
• Two ways of setting slave address
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Wait function in master mode
• Wait function in slave mode
2
Section 14 I
C bus format
function is used.
Examples: HD6432264WTF
⎯ I
⎯ Clocked synchronous serial format: non-addressing format without acknowledge bit, for
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
2
C bus interface is available as an option in H8S/2264 Group. Observe the following note
2
2
C bus interface conforms to and provides a subset of the Philips I
C bus interface data transfer is performed using a data line (SDA) and a clock line (SCL) for
master operation only
2
C bus format: addressing format with acknowledge bit, for master/slave operation
Features
2
C bus format or clocked synchronous serial format
Section 14 I
2
C Bus Interface (IIC) (Supported as an Option
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
by H8S/2264 Group)
2
C bus interface of two channels, while the H8S/2264 Group
Rev. 5.00 Sep. 01, 2009 Page 383 of 656
2
C bus differs partly from the
2
C bus (inter-IC bus)
REJ09B0071-0500