DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 26

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller....................................................................................111
7.1
7.2
Section 8 Data Transfer Controller (DTC) ........................................................115
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Rev. 5.00 Sep. 01, 2009 Page xxiv of l
REJ09B0071-0500
Basic Timing ..................................................................................................................... 111
7.1.1
7.1.2
7.1.3
Bus Arbitration (H8S/2268 Group Only).......................................................................... 113
7.2.1
7.2.2
7.2.3
Features ............................................................................................................................. 115
Register Descriptions ........................................................................................................ 116
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
Activation Sources ............................................................................................................ 122
Location of Register Information and DTC Vector Table ................................................ 123
Operation........................................................................................................................... 126
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
Procedures for Using DTC................................................................................................ 135
8.6.1
8.6.2
Examples of Use of DTC .................................................................................................. 136
8.7.1
8.7.2
Usage Notes ...................................................................................................................... 137
8.8.1
8.8.2
8.8.3
On-Chip Memory Access Timing (ROM, RAM) ................................................ 111
On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF) ........... 112
On-Chip Peripheral Module Access Timing (H'FFFC30 to H'FFFCA3)............. 112
Order of Priority of the Bus Masters.................................................................... 113
Bus Transfer Timing ............................................................................................ 114
Resets and the Bus Controller.............................................................................. 114
DTC Mode Register A (MRA) ............................................................................ 117
DTC Mode Register B (MRB)............................................................................. 118
DTC Source Address Register (SAR).................................................................. 119
DTC Destination Address Register (DAR).......................................................... 119
DTC Transfer Count Register A (CRA) .............................................................. 119
DTC Transfer Count Register B (CRB)............................................................... 119
DTC Enable Register (DTCER) .......................................................................... 120
DTC Vector Register (DTVECR)........................................................................ 121
Normal Mode....................................................................................................... 127
Repeat Mode ........................................................................................................ 128
Block Transfer Mode ........................................................................................... 129
Chain Transfer ..................................................................................................... 131
Interrupts.............................................................................................................. 132
Operation Timing................................................................................................. 132
Number of DTC Execution States ....................................................................... 134
Activation by Interrupt......................................................................................... 135
Activation by Software ........................................................................................ 135
Normal Mode....................................................................................................... 136
Software Activation ............................................................................................. 136
Module Stop Mode Setting .................................................................................. 137
On-Chip RAM ..................................................................................................... 137
DTCE Bit Setting................................................................................................. 137