DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 491

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13. Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode
14.Notes on ACKE Bit and TRS Bit in Slave Mode
15. Notes on Arbitration Lost in Master Mode
When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive
mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the
completion of the transmit or receive operation and a clock may not be output to the SCL bus
line before the ICDR register access operation can take place properly.
When accessing ICDR, always change the setting to the transmit mode before performing a
read operation, and always change the setting to the receive mode before performing a write
operation.
When using the I
1 is received as an acknowledge bit (ACKB = 1) in the transmit mode (TRS = 1), an interrupt
may be generated at the rising edge of the 9th clock cycle if the address does not match.
When performing slave mode operations using the I
the following.
(1) When a 1 is received as an acknowledge bit for the final transmit data after completing a
(2) In the slave mode, change the setting to the receive mode (TRS = 0) before the start
The I
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I
figure 14.27.)
In multi-master mode, a bus conflict could happen. When The I
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
series of transmit operations, clear the ACKE bit in the ICCR register to 0 to initialize the
ACKB bit to 0.
condition is input. To ensure that the switch from the slave transmit mode to the slave
receive mode is accomplished properly, end the transmission as described in figure 14.17.
2
C bus interface recognizes the data in transmit/receive frame as an address when
2
C bus interface erroneously recognizes that the address call has occurred. (See
Section 14 I
2
C bus interface, if an address is received in the slave mode immediately after
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
C bus interface module, make sure to do
Rev. 5.00 Sep. 01, 2009 Page 439 of 656
2
C bus interface is operated in
REJ09B0071-0500