DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 447

IC H8S/2265 MCU FLASH 100TQFP

DF2265TE13V

Manufacturer Part Number
DF2265TE13V
Description
IC H8S/2265 MCU FLASH 100TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2265TE13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2265TE13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.6
I
interface.
Bit
7
6
5
4
2
C bus control register (ICCR) consists of the control bits and interrupt request flags of I
I
Bit Name
ICE
IEIC
MST
TRS
2
C Bus Control Register (ICCR)
Section 14 I
Initial
Value
0
0
0
0
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
R/W
R/W
R/W
R/W
Description
I
When this bit is set to 1, the I
enabled to send/receive data and drive the bus since it is
connected to the SCL and SDA pins. ICMR and ICDR
can be accessed.
When this bit is cleared, the module is halted and
separated from the SCL and SDA pins. SAR and SARX
can be accessed.
I
When this bit is 1, interrupts are enabled by IRIC.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I
format. In slave receive mode, the R/W bit in the first
frame immediately after the start automatically sets these
bits in receive mode or transmit mode by using hardware.
The settings can be made again for the bits that were
set/cleared by hardware, by reading these bits. When the
TRS bit is intended to change during a transfer, the bit
will not be switched until the frame transfer is completed,
including acknowledgement.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
Rev. 5.00 Sep. 01, 2009 Page 395 of 656
2
C bus interface module is
REJ09B0071-0500
2
2
C bus
C bus

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