AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 918

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

39.5.11
Register Name:
Access Type:
Reset Value:
• ENABLE (this bit is a status bit)
0: Module is enabled.
1: Module is disabled.
• DIS_DONE: Module Disable Request has Terminated
1: Disable request has completed. This flag is reset after a read operation.
• SRST: Module Software Reset Request has Terminated
1: Software reset request has completed. This flag is reset after a read operation.
• CDC_PND: Pending Codec Request (this bit is a status bit)
0: Indicates that no Codec request is pending.
1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is
postponed to the next frame.
• VSYNC: Vertical Synchronization
1: Indicates that a Vertical synchronization has been detected since the last read of the status register.
• PXFR_DONE: Preview DMA Transfer has Terminated.
When set to one, this bit indicates that the DATA transfer on the preview channel has completed. This flag is reset after a
read operation.
• CXFR_DONE: Codec DMA Transfer has Terminated.
When set to one, this bit indicates that the DATA transfer on the codec channel has completed. This flag is reset after a
read operation.
• SIP: Synchronization in Progress (this is a status bit)
When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the
clock domain synchronization. This bit is set when this operation occurs. No modification of the channel status is allowed
when this bit is set, to guarantee data integrity.
6438F–ATARM–21-Jun-10
31
23
15
–
–
–
7
–
ISI Status Register
30
22
14
–
–
–
6
–
ISI_SR
Read
0x00000000
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
FR_OVR
SIP
27
19
11
–
3
–
CRC_ERR
VSYNC
SRST
26
18
10
–
2
CXFR_DONE
AT91SAM9G45
DIS_DONE
C_OVR
25
17
9
–
1
PXFR_DONE
CDC_PND
ENABLE
P_OVR
24
16
8
0
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