AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 142
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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19.7.1
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in the
• ULBT: Undefined Length Burst Type
0: Unlimited Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master can only be broken if the Slave
Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the lat-
est, on the next AHB 1 KByte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR
burst.
2: 4-beat Burst
The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end.
3: 8-beat Burst
The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end.
4: 16-beat Burst
The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end.
5: 32-beat Burst
The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end.
6: 64-beat Burst
The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end.
7: 128-beat Burst
The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end.
Unless duly needed the ULBT should be let to its default 0 value for power saving.
6438F–ATARM–21-Jun-10
31
23
15
–
–
–
7
–
Bus Matrix Master Configuration Registers
MATRIX_MCFG0...MATRIX_MCFG10
0xFFFFEA00
Read-write
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
“Write Protect Mode
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
Register”.
AT91SAM9G45
ULBT
25
17
–
–
9
–
1
24
16
–
–
8
–
0
142
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