AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 227
![IC MCU ARM9 APMC 324TFBGA](/photos/12/13/121367/324-tfbga-pkg_sml.jpg)
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
• DBW: Data Bus Width
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge
of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• TDF_MODE: TDF Optimization
1: TDF optimization is enabled.
0: TDF optimization is disabled.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
6438F–ATARM–21-Jun-10
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
• 1: Byte write access type:
• 0: Byte select access type:
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
– The number of TDF wait states is optimized using the setup period of the next read/write access.
– The number of TDF wait states is inserted before the next access begins.
0
0
1
1
0
0
1
1
DBW
PS
0
1
0
1
0
1
0
1
Data Bus Width
8-bit bus
16-bit bus
32-bit bus
Reserved
Page Size
4-byte page
8-byte page
16-byte page
32-byte page
AT91SAM9G45
227
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