AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 265

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

22.7.4
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is
between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles
is between 0 and 15.
• TRRD Active bankA to Active bankB
Reset value is 2.
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles.
Number of cycles is between 1 and 15.
6438F–ATARM–21-Jun-10
31
23
15
7
DDRSDRC Timing 0 Parameter Register
30
22
14
DDRSDRC_T0PR
Read-write
See
6
Table 22-9
TMRD
TRRD
TRCD
TRC
29
21
13
5
28
20
12
4
“DDRSDRC Write Protect Mode Register” on page
REDUCE_WRRD
27
19
11
3
26
18
10
2
TRAS
TWR
TRP
AT91SAM9G45
TWTR
25
17
9
1
275.
24
16
8
0
265