AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1210
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Manufacturer
Quantity
Price
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iv
AT91SAM9G45
21 Static Memory Controller (SMC) ......................................................... 183
22 DDR/SDR SDRAM Controller (DDRSDRC) ......................................... 227
23 Error Corrected Code Controller (ECC) ............................................. 275
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
22.1
22.2
22.3
22.4
22.5
22.6
22.7
23.1
23.2
23.3
23.4
23.5
23.6
23.7
DDR2 Controller ............................................................................................155
External Bus Interface (EBI) ..........................................................................160
Description .....................................................................................................183
I/O Lines Description .....................................................................................183
Multiplexed Signals ........................................................................................183
Application Example ......................................................................................184
Product Dependencies ..................................................................................184
External Memory Mapping .............................................................................185
Connection to External Devices ....................................................................185
Standard Read and Write Protocols ..............................................................190
Automatic Wait States ...................................................................................198
Data Float Wait States ...................................................................................203
External Wait .................................................................................................207
Slow Clock Mode ...........................................................................................213
Asynchronous Page Mode ............................................................................216
Programmable IO Delays ..............................................................................219
Static Memory Controller (SMC) User Interface ............................................220
Description .....................................................................................................227
DDRSDRC Module Diagram .........................................................................228
Product Dependencies ..................................................................................229
Functional Description ...................................................................................234
Software Interface/SDRAM Organization, Address Mapping ........................253
Programmable IO Delays ..............................................................................256
DDR-SDRAM Controller (DDRSDRC) User Interface ...................................256
Description .....................................................................................................275
Block Diagram ...............................................................................................275
Functional Description ...................................................................................275
Error Corrected Code Controller (ECC) User Interface .................................280
Registers for 1 ECC for a page of 512/1024/2048/4096 bytes ......................291
Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes,
8-bit word .......................................................................................................293
Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes,
8-bit word .......................................................................................................301
6438F–ATARM–21-Jun-10
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