ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 90

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9
8042B–AVR–06/10
Accessing Registers in 16-bit Mode
Figure 17-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
Figure 17-9 on page 90
Figure 17-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
In 16-bit mode (the TCWn bit is set to one) the TCNTnH/L and OCRnA/B or TCNTnL/H and
OCRnB/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The
16-bit register must be byte accessed using two read or write operations. The 16-bit
Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers. Accessing the low
byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written
by the CPU, the high byte stored in the temporary register, and the low byte written are both cop-
ied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read
by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same
clock cycle as the low byte is read.
There is one exception in the temporary register usage. In the Output Compare mode the 16-bit
Output Compare Register OCRnA/B is read without the temporary register, because the Output
Compare Register contains a fixed value that is only changed by CPU access. However, in 16-
bit Input Capture mode the ICRn register formed by the OCRnA and OCRnB registers must be
accessed with the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
TCNTn
TCNTn
(clk
(clk
OCRnx
(CTC)
OCRnx
OCFnx
OCFnx
clk
clk
clk
clk
I/O
PCK
I/O
Tn
PCK
Tn
/8)
/8)
shows the setting of OCFnA and the clearing of TCNTn in CTC mode.
OCRnx - 1
TOP - 1
OCRnx
TOP
OCRnx Value
TOP
ATmega16HVB/32HVB
OCRnx + 1
BOTTOM
clk_I/O
BOTTOM + 1
OCRnx + 2
/8)
clk_I/O
/8)
90