ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 199

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.8.8
29.8.9
8042B–AVR–06/10
Reading the Fuse and Lock Bits from Software
Reading the Signature Row from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the LBSET and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the LBSET and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The LBSET and SPMEN bits
will auto-clear upon completion of reading the Lock bits. When LBSET and SPMEN are cleared,
LPM will work as described in the ”AVR Instruction Set” description.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the LBSET and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
LBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the LBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the
signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will
auto-clear 6 cycles after writing to SPMCSR, which is locked for further writing during these
cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set
Manual.
Table 29-3.
Bit
Rd
Bit
Rd
Bit
Rd
Signature Byte Description
Device ID 0, Manufacture ID
Device ID 1, Flash Size
Device ID 2, Device
FOSCCAL
FOSC SEGMENT
Reserved
SLOW RC Period L
SLOW RC Period H
Table 29-3
Table 30-3 on page 209
(1)
Signature Row Addressing.
FHB7
FLB7
(2)
7
–
7
7
(3)
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction
FHB6
FLB6
6
6
6
–
for detailed description and mapping of the Fuse High byte.
BLB12
FLB5
FHB5
5
5
5
BLB11
FLB4
FHB4
4
4
4
BLB02
ATmega16HVB/32HVB
FLB3
FHB3
3
3
3
BLB01
FLB2
FHB2
Z-Pointer Address
2
2
2
Table 30-4 on page 210
00H
02H
04H
01H
03H
05H
06H
07H
FLB1
FHB1
LB2
1
1
1
FLB0
FHB0
LB1
0
0
0
for a
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