ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 143

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.5
8042B–AVR–06/10
BPHCTR – Battery Protection High-current Timing Register
Table 24-3.
Notes:
Note:
• Bit 7:6 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
• Bit 5:0 – HCPT[5:0]: High-current Protection Timing
These bits control the delay of the High-circuit Protection. The High-current Timing can be set
with a step size of 2 ms as shown in
Table 24-4.
Bit
(0xFC)
Read/Write
Initial Value
1. The actual value depends on the actual frequency of the
2. Initial value.
3. An additional delay T
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPOCTR register is written. Any
writing to the BPOCTR register during this period will be ignored.
page
the initialization of the protection circuitry. For the Discharge Over-Current protection, this
applies when enabling the Discharge FET. For Charge Over-Current protection, this applies
when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.1 ms.
Over-current Protection Reaction Time. OCPT[5:0] with corresponding Over-cur-
rent Delay Time.
High-current Protection Reaction Time. HCPT[5:0] with corresponding High-cur-
rent Delay Time.
27. See
R
7
–
0
OCPT[5:0]
HCPT[5:0]
0x02
0x01
0x3E
0x00
0x01
0x03
0x3F
0x00
0x02
0x03
...
”Electrical Characteristics” on page
(2)
(2)
R
6
–
0
Over-current Protection Reaction Time
High-current Protection Reaction Time
d
can be expected after enabling the corresponding FET. This is related to
R/W
5
0
Table 24-4 on page
R/W
4
0
ATmega16HVB/32HVB
R/W
3
0
HCPT[5:0]
230.
143.
R/W
(30.5 - 31.0 ms) + T
(31.0 - 31.5 ms) + T
”Ultra Low Power RC Oscillator” on
2
0
(0.0 - 0.5 ms) + T
(0.0 - 0.5 ms) + T
(0.5 - 1.0 ms) + T
(1.0 - 1.5 ms) + T
(0 - 2 ms) + T
(0 - 2 ms) + T
(2 - 4 ms) + T
(4 - 6 ms) + T
(1)
(1)
Typ
Typ
R/W
...
1
0
d
d
d
d
(3)
(3)
(3)
(3)
d
d
d
d
(3)
(3)
(3)
(3)
R/W
d
d
(3)
(3)
0
1
BPHCTR
143