ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 241

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8042B–AVR–06/10
Figure 32-6. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 32-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Table 32-18. Parallel Programming Characteristics
Symbol
V
I
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
PP
XTAL1
DATA
PAGEL
XTAL1
BS1
XA0
XA1
DATA
OE
BS1
XA0
XA1
1. The timing requirements shown in
1. The timing requirements shown in
ing operation.
ing operation.
Parameter
Programming Enable Voltage (RESET input)
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
Timing Requirements
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 32-5
Figure 32-5
t
XLXH
t
BVDV
ATmega16HVB/32HVB
(i.e., t
(i.e., t
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
LOAD DATA
, t
, t
XHXL
XHXL
11.5
Min
200
150
67
67
, and t
, and t
t
t
OHDZ
PLXH
Typ
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
ADDR1 (Low Byte)
Max
12.5
250
Units
μA
ns
ns
ns
ns
V
(1)
241