ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 145

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.8
24.7.9
24.7.10
8042B–AVR–06/10
BPCOCD – Battery Protection Charge-Over-current Detection Level Register
BPDHCD – Battery Protection Discharge-High-current Detection Level Register
BPCHCD – Battery Protection Charge-High-current Detection Level Register
• Bits 7:0 –COCDL[7:0]: Charge Over-current Detection Level
These bits sets the R
Table 24-5 on page
Note:
• Bits 7:0 – DHCDL[7:0]: Discharge High-current Detection Level
These bits sets the R
Table 24-5 on page
Note:
• Bits 7:0 –CHCDL[7:0]: Charge High-current Detection Level
These bits sets the R
Table 24-5 on page
Note:
Table 24-5.
Bit
(0xF7)
Read/Write
Initial Value
Bit
(0xF8)
Read/Write
Initial Value
Bit
(0xF9)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCOCD register is written. Any
writing to the BPCOCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDHCD register is written. Any
writing to the BPDHCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCHCD register is written. Any
writing to the BPCHCD register during this period will be ignored.
DL[7:0]
0xF3
0xF4
0xF5
DL[7:0] with corresponding R
Registers (BPSCD, BPDOCD, BPCOCD, BPDHCD, BPCHCD).
R/W
R/W
R/W
7
1
7
1
7
1
145.
145.
145.
SENSE
SENSE
SENSE
R/W
R/W
R/W
6
1
6
1
6
1
voltage level for detection of DischargeHigh-current, as defined in
voltage level for detection of Charge Over-current, as defined in
voltage level for detection of Charge High-current, as defined in
Current Protection Detection Levels
Min.
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
SENSE
4
1
4
1
4
1
COCDL[7:0]
DHCDL[7:0]
CHCDL[7:0]
voltage levels for all Current Detection Level
R/W
ATmega16HVB/32HVB
R/W
R/W
3
0
3
0
3
0
Typ. (mV)
20
25
30
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1
Max.
BPCOCD
BPDHCD
BPCHCD
145