ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 144

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.6
24.7.7
8042B–AVR–06/10
BPSCD – Battery Protection Short-circuit Detection Level Register
BPDOCD – Battery Protection Discharge-Over-current Detection Level Register
Table 24-4.
Notes:
Note:
• Bits 7:0 – SCDL[7:0]: Short-circuit Detection Level
These bits sets the R
as defined in
Note:
• Bits 7:0 – DOCDL[7:0]: Discharge Over-current Detection Level
These bits sets the R
Table 24-5 on page
Note:
Bit
(0xF5)
Read/Write
Initial Value
Bit
(0xF6)
Read/Write
Initial Value
1. The actual value depends on the actual frequency of the
2. Initial value.
3. An additional delay T
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPHCTR register is written. Any
writing to the BPHCTR register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPSCD register is written. Any
writing to the BPSCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDOCD register is written. Any
writing to the BPDOCD register during this period will be ignored.
page
the initialization of the protection circuitry. For the Discharge High-Current protection, this
applies when enabling the Discharge FET. For Charge High-Current protection, this applies
when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.2 ms.
Table 24-5 on page
High-current Protection Reaction Time. HCPT[5:0] with corresponding High-cur-
rent Delay Time.
R/W
R/W
27. See
7
1
7
1
145.
SENSE
0x3E
0x3F
SENSE
...
”Electrical Characteristics” on page
R/W
R/W
6
1
6
1
voltage level for detection of Short-circuit in the Discharge Direction,
voltage level for detection of Discharge Over-current, as defined in
High-current Protection Reaction Time
d
can be expected after enabling the corresponding FET. This is related to
145.
R/W
R/W
5
1
5
1
R/W
R/W
4
1
4
1
DOCDL[7:0]
SCDL[7:0]
R/W
ATmega16HVB/32HVB
R/W
3
0
3
0
230.
R/W
R/W
(122 - 124 ms) + T
(124 - 126 ms) + T
2
0
”Ultra Low Power RC Oscillator” on
2
0
(1)
R/W
R/W
...
1
1
1
1
d
d
R/W
R/W
(3)
(3)
0
1
0
1
BPDOCD
BPSCD
144