ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 154

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26. Cell Balancing
26.1
8042B–AVR–06/10
Overview
ATmega16HVB/32HVB incorporates cell balancing FETs. The chip provides one cell balancing
FET for each battery cell in series. The FETs are directly controlled by the application software,
allowing the cell balancing algorithms to be implemented in software. The FETs are connected
in parallel with the individual battery cells. The cell balancing is illustrated in
ure shows a four-cell configuration. The cell balancing FETs are disabled in the Power-off mode.
For typical current through the Cell Balancing FETs, see
230.
The Cell Balancing FETs are controlled by the CBCR. Neighbouring FETs cannot be simultane-
ously enabled. If trying to enable two neighbouring FETs, both will be disabled.
Figure 26-1. Cell Balancing
RP
RP
RP
RP
RP
T
T
T
T
CB
CB
CB
CB
PV4
PV3
PV2
PV1
NV
Level
Shift
Level
Shift
Level
Shift
Level
Shift
ATmega16HVB/32HVB
Control Register
Cell Balancing
”Electrical Characteristics” on page
Figure
26-1. The fig-
154