ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 85

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5.3
17.5.4
8042B–AVR–06/10
16-bit Mode
Clear Timer on Compare Match (CTC) 16-bit Mode
zero when the counter value (TCNTn) matches the OCRnA. The OCRnA defines the top value
for the counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
(TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then coun-
ter (TCNTn) is cleared.
Figure 17-3. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCRnA is lower than the current
value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur. As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
In 16-bit mode, the counter (TCNTnH/L) is a incrementing until it overruns when it passes its
maximum 16-bit value (MAX = 0xFFFF) and then restarts from the bottom (0x0000), see
17-2 on page 84
cycle as the TCNTnH/L becomes zero. The TOVn Flag in this case behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that
automatically clears the TOVn Flag, the timer resolution can be increased by software. There
are no special cases to consider in the Normal mode, a new counter value can be written any-
time. The Output Compare Unit can be used to generate interrupts at some given time.
In Clear Timer on Compare 16-bit mode, OCRAnA/B Registers are used to manipulate the coun-
ter resolution, see
zero when the counter value (TCNTn) matches OCRnA/B, where OCRnB represents the eight
most significant bits and OCRnA represents the eight least significant bits. OCRnA/B defines the
top value of the counter, hence also its resolution. This mode allows greater control of the Com-
pare Match output frequency. It also simplifies the operation of counting external events.
An interrupt can be generated each time the counter reaches the TOP value by using the
OCFnA flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the
TOP value. However, changing the TOP to a value close the BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCRnA/B is lower than the current
TCNTn
Period
for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock
Table 17-2 on page 84
1
2
for bit settings. In CTC mode the counter is cleared to
3
Figure 17-3 on page
ATmega16HVB/32HVB
4
OCnx Interrupt Flag Set
85. The counter value
Table
85