DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 40

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 3-2:
DS70657F-page 40
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1:
SATA
R/W-0
R/W-0
VAR
2:
3:
(1)
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
This bit is always read as ‘0’.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing enabled
0 = Fixed exception processing enabled
Unimplemented: Read as ‘0’
US<1:0>: DSP Multiply Unsigned/Signed Control bits
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
SATB
R/W-0
U-0
—
CORCON: CORE CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
SATDW
R/W-0
R/W-1
US<1:0>
(1)
ACCSAT
(1)
R/W-0
R/W-0
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
(1,2)
‘0’ = Bit is cleared
(1)
EDT
(3)
IPL3
R/W-0
R/C-0
(1,2)
(1)
(3)
(1)
SFA
R-0
R-0
 2011-2012 Microchip Technology Inc.
(1)
x = Bit is unknown
DL<2:0>
RND
R/W-0
R-0
(1)
(1)
R/W-0
IF
R-0
(1)
bit 8
bit 0