DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 269

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 18-1:
 2011-2012 Microchip Technology Inc.
bit 1
bit 0
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Standard Buffer Mode:
Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer Mode:
Automatically set in hardware when CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a
transfer from SPIxSR.
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
DS70657F-page 269