DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 215

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DSPIC33EP128MC504-I/PT

Manufacturer Part Number
DSPIC33EP128MC504-I/PT
Description
Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
Manufacturer
Microchip Technology
Type
dsPIC33E/PIC24Er
Datasheet

Specifications of DSPIC33EP128MC504-I/PT

Rohs
yes
Core
dsPIC33E
Data Bus Width
16 bit
Program Memory Size
128 KB
Data Ram Size
16 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
35
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
70 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Family / Core
dsPIC33E/PIC24E
Interface Type
CAN, I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33EP128MC504-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
14.2
REGISTER 14-1:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9-7
bit 6-5
bit 4
bit 3
bit 2-0
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
U-0
U-0
Input Capture Registers
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Stop in Idle Control bit
1 = Input capture will Halt in CPU Idle mode
0 = Input capture will continue to operate in CPU Idle mode
ICTSEL<12:10>: Input Capture Timer Select bits
111 = Peripheral clock (F
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
010 = T4CLK is the clock source of the ICx
001 = T2CLK is the clock source of the ICx
000 = T3CLK is the clock source of the ICx
Unimplemented: Read as ‘0’
ICI<1:0>: Number of Captures per Interrupt Select bits
(this field is not used if ICM<2:0> = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow occurred
0 = No input capture buffer overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only in CPU Sleep and Idle mode (rising edge detect
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every edge, rising and falling (Edge Detect mode (ICI<1:0>) is not used in this
000 = Input Capture module is turned off
R/W-0
U-0
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
only, all other control bits are not applicable)
mode)
ICI<1:0>
HC = Cleared by Hardware
W = Writable bit
ICSIDL
R/W-0
R/W-0
P
) is the clock source of the ICx
R/HC/HS-0
R/W-0
ICOV
ICTSEL<2:0>
HS = Set by Hardware
U = Unimplemented bit, read as ‘0’
R/HC/HS-0
ICBNE
R/W-0
R/W-0
R/W-0
ICM<2:0>
R/W-0
‘0’ = Bit is cleared
U-0
DS70657F-page 215
R/W-0
U-0
bit 8
bit 0

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