DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 139

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

FIGURE 8-2:
8.1
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
8.1.1
• Section 22. “Direct Memory Access (DMA)”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33E/PIC24E Family Reference
• Development Tools
 2011-2012 Microchip Technology Inc.
Note:
(DS70348)
Manuals Sections
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
DMA Resources
Note: CPU and DMA address buses are not shown
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
KEY RESOURCES
for clarity.
SRAM
Arbiter
CPU
DMA CONTROLLER BLOCK DIAGRAM
DMA Controller
Peripheral
Non-DMA
CPU Peripheral X-Bus
0 1
Channels
DMA
2 3
Peripheral Indirect Address
DMA X-Bus
8.2
Each DMAC Channel x (where x = 0 through 3)
contains the following registers:
• 16-bit DMA Channel Control register (DMAxCON)
• 16-bit DMA Channel IRQ Select register
• 32-bit DMA RAM Primary Start Address register
• 32-bit DMA RAM Secondary Start Address
• 16-bit DMA Peripheral Address register (DMAxPAD)
• 14-bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA, and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
Interrupt Controller
IRQ to DMA and
Peripheral 2
CPU
Ready
Modules
DMA
DMAC Registers
DMA
Peripheral 1
CPU
Ready
DMA
DMA
Interrupt Controller
Peripheral 3
IRQ to DMA and
CPU
Ready
Modules
DMA
DMA
and Interrupt
IRQ to DMA
Controller
Modules
DS70657F-page 139