DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 328

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 23-5:
DS70657F-page 328
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-9
bit 8
bit 7-3
bit 2-1
bit 0
Note 1:
U-0
U-0
—
—
2:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2,
and 3.
If the Op amp is selected (OPMODE bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXB bits
In 12-bit mode, (AD21B = 1), CH123NB is unimplemented and is read as ‘0’
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit
In 12-bit mode, (AD21B = 1), CH123SB is unimplemented and is read as ‘0’
Unimplemented: Read as ‘0’
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXA bits
In 12-bit mode, (AD21B = 1), CH123NA is unimplemented and is read as ‘0’
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample MUXA bit
In 12-bit mode, (AD21B = 1), CH123SA is unimplemented and is read as ‘0’
11
10
0x
1
0
11
10
0x
1
0
Value
Value
Value
Value
(2)
(1,2)
(2)
(1,2)
(1,2)
(1,2)
U-0
U-0
—
—
AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
OA3/AN6
OA1/AN3
OA2/AN0
OA3/AN6
OA1/AN3
OA2/AN0
V
V
CH1
AN9
CH1
CH1
AN9
CH1
REFL
REFL
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
ADC Channel
ADC Channel
ADC Channel
ADC Channel
OA2/AN0
OA2/AN0
V
V
AN10
AN10
CH2
AN7
CH2
AN1
CH2
AN7
CH2
AN1
REFL
REFL
U-0
U-0
—
—
OA3/AN6
OA3/AN6
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
V
V
AN11
AN11
CH3
CH3
CH3
CH3
AN8
AN2
AN8
AN2
REFL
REFL
U-0
U-0
—
—
R/W-0
R/W-0
CH123NB<1:0>
CH123NA<1:0>
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
Figure 23-1
CH123SB
CH123SA
R/W-0
R/W-0
bit 8
bit 0