DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 345

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 24-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER
REGISTER 24-13: PTGQUEx: PTG STEP QUEUE REGISTERS (x = 0-7)
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 4-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
R/W-0
R/W-0
U-0
U-0
—
—
2:
3:
This register is read only when the PTG module is executing step commands (PTGEN = 1 and
PTGSTRT = 1).
This register is read only when the PTG module is executing step commands (PTGEN = 1 and
PTGSTRT = 1).
Refer to
The step registers maintain their values on any type of reset.
Unimplemented: Read as ‘0’
PTGQPTR<4:0>: PTG Step Queue Pointer Register bits
This register points to the currently active step command in the step queue.
STEP(2x +1)<7:0>: PTG Step Queue Pointer Register bits
A queue location for storage of the STEP(2x +1) command byte.
STEP(2x)<7:0>: PTG Step Queue Pointer Register bits
A queue location for storage of the STEP(2x) command byte.
R/W-0
R/W-0
Table 24-1
U-0
U-0
—
—
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
for the STEP command encoding.
R/W-0
R/W-0
U-0
U-0
—
—
STEP(2x +1)<7:0>
R/W-0
R/W-0
R/W-0
STEP(2x)<7:0>
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
U-0
—
(2)
(2)
(2)
PTGQPTR<4:0>
(2)
R/W-0
R/W-0
R/W-0
U-0
—
(1)
(1,3)
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
U-0
—
DS70657F-page 345
R/W-0
R/W-0
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0