DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 230

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
16.3
REGISTER 16-1:
DS70657F-page 230
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
Note 1:
SYNCEN
R/W-0
R/W-0
PTEN
2:
PWM Control Registers
(1)
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
See
Section 24.0 “Peripheral Trigger Generator (PTG) Module”
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
EIPU: Enable Immediate Period Updates bit
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCI1/SYNCO1 polarity is inverted (active-low)
0 = SYNCI1/SYNCO1 is active-high
SYNCOEN: Primary Time Base Sync Enable bit
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
SYNCEN: External Time Base Synchronization Enable bit
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
SYNCSRC<2:0>: Synchronous Source Selection bits
111 = Reserved
•
•
•
100 = Reserved
011 = PTGO17
010 = PTGO16
001 = Reserved
000 = SYNCI 1 input from PPS
R/W-0
U-0
—
PTCON: PWM TIME BASE CONTROL REGISTER
SYNCSRC<2:0>
HC = Cleared in Hardware HS = Set in Hardware
W = Writable bit
‘1’ = Bit is set
(2)
(2)
PTSIDL
R/W-0
R/W-0
(1)
HS/HC-0
SESTAT
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
SEIEN
R/W-0
R/W-0
(1)
(1)
(1)
(1)
EIPU
R/W-0
R/W-0
for information on this selection.
SEVTPS<3:0>
(1)
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
SYNCPOL
R/W-0
R/W-0
(1)
(1)
SYNCOEN
R/W-0
R/W-0
bit 8
bit 0
(1)