DSPIC33EP128MC504-I/PT Microchip Technology, DSPIC33EP128MC504-I/PT Datasheet - Page 108

• Manufacturer Part Number: DSPIC33EP128MC504-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 44P OpAmps
• Manufacturer: Microchip Technology
• Type: dsPIC33E/PIC24Er

Specifications of DSPIC33EP128MC504-I/PT

• Rohs: yes
• Core: dsPIC33E
• Data Bus Width: 16 bit
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 70 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33E/PIC24E
• Interface Type: CAN, I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
4.4.3
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA, and the ICD module. In
the event of coincidental access to a bus by the bus
masters, the arbiter determines which bus master
access has the highest priority. The other bus masters
are suspended and processed after the access of the
bus by the bus master with the highest priority.
By default, the CPU is bus master 0 (M0) with the
highest priority, and the ICD is bus master 4 (M4) with
the lowest priority. The remaining bus master (DMA
controller) is allocated to M3, (M1 and M2 are reserved
and cannot be used). The user application may raise or
lower the priority of the DMA controller to be above that
of the CPU by setting the appropriate bits in the EDS
Bus Master Priority Control (MSTRPR) register. All bus
masters with raised priorities will maintain the same
priority relationship relative to each other (i.e., M1
being highest and M3 being lowest with M2 in
between). Also, all the bus masters with priorities below
FIGURE 4-18:
DS70657F-page 108
MSTRPR<15:0>
DATA MEMORY ARBITRATION AND
BUS MASTER PRIORITY
ARBITER ARCHITECTURE
DMA
M0
Reserved
Data Memory Arbiter
M1
that of the CPU maintain the same priority relationship
relative to each other. The priority schemes for bus
masters with different MSTRPR values are tabulated in
Table
This bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization, or
dynamically in response to real-time events.
TABLE 4-62:
Note 1:
SRAM
M2
M0 (highest)
M4 (lowest)
Priority
4-62.
M1
M2
M3
M3
ICD
All other values of MSTRPR<15:0> are
Reserved.
M4
ARBITER PRIORITY
DATA MEMORY BUS
 2011-2012 Microchip Technology Inc.
MSTRPR<15:0> Bit Setting
Reserved
Reserved
0x0000
DMA
CPU
ICD
CPU
Reserved
Reserved
0x0020
DMA
CPU
ICD
(1)