AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 75

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

DETAILED FUNCTIONS
1 Mbps HomePNA PHY
The integrated HomePNA transceiver is a physical
layer device supporting the HomePNA specification 1.0
for home phone line networking. It provides all of the
PHY layer functions required to support 1 Mbps data
transfer speeds over common residential phone wiring.
All data bits are encoded into the relative time position
of a pulse with respect to the previous one, the wave-
form on the wire consists of a 7.5 MHz carrier sinusoid
enclosed within an exponential (bell shaped) envelope.
The waveform is produced by generating four 7.5 MHz
square wave cycles and passing them through a band-
pass filter.
The HomePNA PHY frame consists of a HomePNA
header that replaces the normal Ethernet 64-bit pream-
ble and delimiter and is prepended to a standard Ether-
net packet starting with the destination address and
ending with the CRC.
Only the PHY layer and its parameters are modified
from that of the standard Ethernet implementation. The
HomePNA PHY layer is designed to operate with the
internal Ethernet MAC layer controller implementing all
the CSMA/CD protocol features.
The frame begins with a characteristic SYNC interval
that delineates the beginning of a HomePNA frame fol-
lowed by an Access ID (AID) which encodes 8 bits of
Access ID and 4 bits of control word. The Access ID is
used to detect collisions and is dynamically assigned,
while the control word carries speed and power infor-
mation.
The AID is followed by a silence interval, then 32 bits of
data reserved for PHY layer communication. These
bits are accessible via HPR20 and HPR21 and are for
future use.
The data encoding consists of two symbol types: an
AID symbol and a data symbol. The AID symbol is al-
ways transmitted at the same speed and encodes two
bits that determine the pulse position (one of four) rel-
ative to the previous pulse. The access symbol interval
is fixed.
Am79C978
The data symbol interval is variable. The arriving bit
stream is blocked into from 3 to 6 bit blocks according
to a proprietary (RLL25™) algorithm. The bits in each
block are then used to encode a data symbol. Each
symbol consists of a Data Inter Symbol Blanking Inter-
val (DISBI) and then a pulse at one of twenty-five pos-
sible positions. The bits in the data block determine the
pulse position. Immediately after the pulse a new sym-
bol interval begins. During the DISBI the receiver ig-
nores all incoming pulses to allow network reflections
to die out.
Any station may be programmed to assume the role of
a PHY master and remotely command, via the control
word, the rest of the units on the network to change
their transmit speed or power level.
Many of the framing parameters are programmable in
the HomePNA PHY and will allow future modifications
to both transmission speed as well as noise and reflec-
tion rejection algorithms.
Two default speeds are provided, low at 0.7 Mbps and
high at 1 Mbps. The center frequency is also program-
mable for future use.
HomePNA PHY Medium Interface
Framing
The HomePNA frame on the phone wire network con-
sists of a header generated in the PHY prepended to
an IEEE 802.3 Ethernet data packet received from the
MAC layer. See Figure 37.
When transmitting on the phone wire pair, the
HomePNA PHY first receives an Ethernet MAC frame
from the MAC. The 8 octets of preamble and delimiter
are stripped off and replaced with the HomePNA PHY
header described below, then transmitted LSB first on
the phone wire network.
During a receive operation, the reverse process is ex-
ecuted. When a HomePNA frame is received by the
PHY, the header is stripped off and replaced with the
four octets of preamble and delimiter of the IEEE 802.3
Ethernet MAC frame specification and then passed on
to the MAC layer.
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