AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 128

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

2
1
0
128
LOOP
0
0
1
LOOP
DTX
DRX
Table 30. Loopback Configuration
INTL
0
0
0
MIIILP
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit was called DTCR in the
LANCE (Am7990) device.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
Am79C978 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows in Table
30.
Am79C978 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
Am79C978 controller not access-
Loopback Enable allows the
Disable
Disable Receiver results in the
Refer to Loopback Operation
section for more details.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
0
1
0
DXMTFCS
Normal Operation
Internal Loop
External Loop
Transmit
Function
is
results
set
and
Am79C978
in
CSR16: Initialization Block Address Lower
Bit
31-16 RES
15-0
CSR17: Initialization Block Address Upper
Bit
31-16 RES
15-0
CSR18: Current Receive Buffer Address Lower
Bit
31-16 RES
15-0
CSR19: Current Receive Buffer Address Upper
Bit
31-16 RES
Name
IADRL
Name
IADRH
Name
CRBAL
Name
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0 will set
RXON bit (CSR0 bit 5) if STRT
(CSR0 bit 1) is asserted.
Description
zeros and read as undefined.
This register is an alias of CSR1.
Description
zeros and read as undefined.
This register is an alias of CSR2.
Description
zeros and read as undefined.
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
Description
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as