AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 130

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

15-0
CSR27: Next Receive Descriptor Address Upper
Bit
31-16
15-0
CSR28: Current Receive Descriptor Address Lower
Bit
31-16
15-0
CSR29: Current Receive Descriptor Address Upper
Bit
31-16
15-0
130
NRDAL
Name
RES
NRDAU
Name
RES
CRDAL
Name
RES
CRDAU
next receive descriptor address
pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
next receive descriptor address
pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current receive descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current receive descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Am79C978
CSR30: Base Address of Transmit Ring Lower
Bit
31-16 RES
15-0
CSR31: Base Address of Transmit Ring Upper
Bit
31-16 RES
15-0
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16 RES
15-0
CSR33: Next Transmit Descriptor Address Upper
Bit
31-16 RES
15-0
Name
BADXL
Name
BADXU
Name
NXDAL
Name
NXDAU
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
zeros and read as undefined.
base address of the Transmit
Ring.
Description
zeros and read as undefined.
base address of the Transmit
Ring.
Description
zeros and read as undefined.
next transmit descriptor address
pointer.
Description
zeros and read as undefined.
next transmit descriptor address
pointer.
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
Contains the upper 16 bits of the
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
Contains the upper 16 bits of the