AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 129

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

15-0
CSR20: Current Transmit Buffer Address Lower
Bit
31-16
15-0
CSR21: Current Transmit Buffer Address Upper
Bit
31-16
15-0
CSR22: Next Receive Buffer Address Lower
Bit
31-16
15-0
CRBAU
Name
RES
CXBAL
Name
RES
CXBAU
Name
NRBAL
RES
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current transmit buffer address
from which the Am79C978 con-
troller is transmitting.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
current transmit buffer address
from which the Am79C978 con-
troller is transmitting.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
These bits are read/write acces-
sible only when either the STOP
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
Am79C978
CSR23: Next Receive Buffer Address Upper
Bit
31-16 RES
15-0
CSR24: Base Address of Receive Ring Lower
Bit
31-16 RES
15-0
CSR25: Base Address of Receive Ring Upper
Bit
31-16 RES
15-0
CSR26: Next Receive Descriptor Address Lower
Bit
31-16 RES
Name
NRBAU
Name
BADRL
Name
BADRU
Name
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
zeros and read as undefined.
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
Description
zeros and read as undefined.
Contains the lower 16 bits of the
base address of the Receive
Ring.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
base address of the Receive
Ring.
Description
zeros and read as undefined.
Reserved locations. Written as
Contains the upper 16 bits of the
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
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