AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 42

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

Master Bus Interface Unit
The master Bus Interface Unit (BIU) controls the acqui-
sition of the PCI bus and all accesses to the initializa-
tion block, descriptor rings, and the receive and
transmit buffer memory. Table 7 shows the usage of
PCI commands by the Am79C978 controller in master
mode.
42
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
C[3:0]
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Table 7. Master Commands
Command
DEVSEL
FRAME
PERR
TRDY
IRDY
C/BE
CLK
PAR
AD
Figure 12. Slave Cycle Data Parity Error Response
Not used
Not used
Not used
Not used
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
Write to the descriptor
rings and to the receive
buffer
1
2
Use
ADDR
CMD
3
PAR
4
Am79C978
5
DATA
BE
Bus Acquisition
The microcode will determine when a DMA transfer
should be initiated. The first step in any bus master
transfer is to acquire ownership of the bus. This task is
handled by synchronous logic within the BIU. Bus own-
ership is requested with the REQ signal and ownership
is granted by the arbiter through the GNT signal.
Figure 13 shows the Am79C978 controller bus acquisi-
tion. REQ is asserted and the arbiter returns GNT while
ano ther bu s m ast er is tra ns fer ri ng d ata. Th e
Am79C978 controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The Am79C978 controller
does not use address stepping which is reflected by
1010
1011
1100
1101
1110
1111
6
Table 7. Master Commands (Continued)
PAR
7
Configuration Read Not used
Configuration Write Not used
Memory Read
Multiple
Dual Address Cycle Not used
Memory Read Line
Memory Write
Invalidate
8
9
10
Read of the transmit
buffer in burst mode
Read of the transmit
buffer in burst mode
Not used
22206B-15