AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 178

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

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XMTE
POWER
RCVE
SPEED
COLE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network.
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
S_RESET or setting the STOP
bit.
This bit is always read/write ac-
cessible. XMTE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
This bit is always read/write ac-
cessible. RCVE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
This bit is always read/write ac-
cessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Am79C978
BCR49: PHY Select
This register defines which PHY will be able to send
and receive data over the MII interface. Bits 15:8 are
updated whenever the EEPROM is read, and bits 6:0
are updated only if bit 7 is cleared. The bits are defined
as follows:
Bit
15
14-10 RES
9-8
7
6-2
1-0
BCR50-BCR55: Reserved Locations
These registers must be 00h.
PC_NET
PHY_SEL_Default
PHY_SEL_Lock
RES
PHY_SEL
Name
PCnet mode. This bit must al-
ways be set.
Reserved locations. These bits
must be written as zeros.
PHY Select Default. These bits
store the desired default PHY.
These bits have no effect on the
operation of the device and are
provided only as a storage loca-
tion.
PHY Select Lock. Setting this bit
prevents the PHY_SEL bits from
being overwritten by subsequent
soft resets. The user may write
this bit at any time. It is cleared
during Power-On Reset.
Reserved. Must be written as
zero.
PHY Select. These bits define the
active PHY as follows:
00
01
10
11
Description
10BASE-T PHY
HomePNA PHY
External PHY
Reserved/Undefined