AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 140

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

.
7-0
CSR82: Transmit Descriptor Address Pointer
Lower
Bit
31-16 RES
15-0
CSR84: DMA Address Register Lower
Bit
31-16 RES
140
Table 34. Transmit Watermark Programming
XMTFW[1:0]
DMATC[7:0] DMA Transfer Counter. Writing
TXDAPL
Name
Name
00
01
10
11
and reading to this field has no ef-
fect.
MIN_GNT in the PCI configura-
tion space.
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
transmit descriptor address cor-
responding to the last buffer of
the previous transmit frame. If the
previous transmit frame did not
use buffer chaining, then TXDA-
PL contains the lower 16 bits of
the previous frame’s transmit de-
scriptor address.
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. XMTFW is
set to a value of 00b (16 bytes) af-
ter H_RESET or S_RESET and
is unaffected by STOP.
When both the STOP or SPND
bits are cleared, this register is
updated by the Am79C978 con-
troller immediately before a trans-
mit descriptor write.
Read accessible always. Write
accessible through the PXDAL
bits (CSR60) when the STOP or
SPND bit is set. TXDAPL is set to
0 by H_RESET and are unaffect-
ed by S_RESET or STOP.
Description
Description
Use
Bytes Available
Reserved
MAX_LAT
108
16
64
and
Am79C978
15-0
CSR85: DMA Address Register Upper
Bit
31-16 RES
15-0
CSR86: Buffer Byte Counter
Bit
31-16 RES
15-12 RES
11-0
DMABAL
DMABAU
DMABC
Name
Name
This register contains the lower
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAL register is undefined
until the first Am79C978 control-
ler DMA operation.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
This register contains the upper
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAU register is undefined
until the first Am79C978 control-
ler DMA operation.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved. Read and written with
ones.
DMA Byte Count Register. Con-
tains the two's complement of the
current size of the remaining
transmit or receive buffer in
bytes. This register is increment-
ed by the Bus Interface Unit. The
Description
Description