AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 35

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

MII Management Frames
MII management frames are automatically generated
by the Am79C978 controller and conform to the MII
clause in the IEEE 802.3u standard.
The start of the frame may be a preamble of 32 ones
(unless bit 6 of register equals 1) and guarantees that
all of the external PHYs are synchronized on the same
interface. See Figure 2. Loss of synchronization is pos-
This is followed by a start field (ST) and an operation
field (OP). The operation field (OP) indicates whether
the Am79C978 controller is initiating a read or write op-
eration. This is followed by the external PHY address
(PHYAD) and the register address (REGAD) pro-
grammed in BCR33. The PHY address of 1D,1E, and
1F are reserved and should not be used. The external
PHY may have a larger address space starting at 10h
- 1Fh. This is the address range set aside by the IEEE
as vendor usable address space and will vary from
vendor to vendor. This field is followed by a bus turn-
around field. During a read operation, the bus turn-
around field is used to determine if the external PHY is
responding correctly to the read request or not. The
Am79C978 controller will tri-state the MDIO for both
MDC cycles.
During the second cycle, if the external PHY is syn-
chronized to the Am79C978 controller, the external
PHY will drive a 0. If the external PHY does not drive a
0, the Am79C978 controller will signal a MREINT
(CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set
to a 1, indicating the Am79C978 controller had an MII
management frame read error and that the data in
BCR34 is not valid. The data field to/from the external
PHY is read or written into the BCR34 register. The last
field is an IDLE field that is necessary to give ample
time for drivers to turn off before the next access. The
Am79C978 controller will drive the MDC to 0 and tri-
state the MDIO anytime the MII Management Port is
not active.
To help to speed up the reading and of writing the MII
management frames to the external PHY, the MDC can
1111....1111
Preamble
Bits
32
Bits
ST
01
2
Figure 2. Frame Format at the MII Interface Connection
10 Rd
01 Wr
OP
Bits
2
Address
PHY
Bits
5
Am79C978
sible due to the hot-plugging capability of the exposed
MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C978 controller will then drop the creation of the
preamble stream until a reset occurs, receives a read
error, or the external PHY is disconnected.
be sped up to 5 MHz by setting the FMDC bits in
BCR32. The IEEE 802.3 specification requires use of
the 2.5-MHz clock rate, but 5 MHz is also available for
the user. The 5-MHz clock rate can be used for an ex-
posed MII with one external PHY attached. The 2.5-
MHz clock rate is intended to be used when multiple
external PHYs are connected to the MII Management
Port or if compliance to the IEEE 802.3u standard is re-
quired.
Auto-Poll External PHY Status Polling
As defined in the IEEE 802.3 standard, the external
PHY attached to the Am79C978 controller’s MII has no
way of communicating important timely status informa-
tion back to Am79C978 controller. The Am79C978
controller has no way of knowing that an external PHY
has undergone a change in status without polling the
MII status register. To prevent problems from occurring
with i nadequate host or software polling, the
Am79C978 controller will Auto-Poll when APEP
(BCR32, bit 11) is set to 1 to insure that the most cur-
rent information is available. See 10BASE-T PHY Man-
agement Registers for the bit descriptions of the MII
Status Register. The contents of the latest read from
the external PHY will be stored in a shadow register in
the Auto-Poll block. The first read of the MII Status
Register will just be stored, but subsequent reads will
be compared to the contents already stored in the
shadow register. If there has been a change in the con-
tents of the MII Status Register, a MAPINT (CSR7, bit
5) interrupt will be generated on INTA if the MAPINTE
(CSR7, bit 4) is set to 1. The Auto-Poll features can be
disabled if software driver polling is required.
Register
Address
Bits
5
Z0 Rd
10 Wr
Bits
TA
2
Data
Bits
16
Idle
Bit
1
Z
22206B-5
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