AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 46

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

ample, the memory system extends the data phase of
the first access by one wait state. The following three
data phases take one clock cycle each, which is deter-
mined by the timing of TRDY. The example assumes
that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ
is not deasserted until the next to last data phase is fin-
ished.
Target Initiated Termination
When the Am79C978 controller is a bus master, the cy-
cles it produces on the PCI bus may be terminated by
the target in one of three different ways: disconnect
with data transfer, disconnect without data transfer, and
target abort.
46
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
Figure 17. Burst Write Transfer (EXTREQ = 1)
1
DEVSEL is sampled
2
ADDR
0111
3
Am79C978
PAR
4
DATA
Disconnect With Data Transfer
Figure 18 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP
is asserted on clock 4 to start the termination se-
quence. Data is still transferred during this cycle, since
both IRDY and TRDY are asserted. The Am79C978
controller terminates the current transfer with the deas-
sertion of FRAME on clock 5 and of IRDY one clock
later. It finally releases the bus on clock 7. If it wants to
transfer more data, the Am79C978 controller will again
request the bus after two clock cycles. The starting ad-
dress of the new transfer will be the address of the next
non-transferred data.
5
PAR
DATA
BE
6
DATA
PAR
7
DATA
PAR
8
PAR
9
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