AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 111

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

14-13 DATA_SCALE
12-9
8
7-2
1-0
PWR_STATE Power State. This 2-bit field is
RES
PME_EN
DATA_SEL Data Select. This optional 4-bit
field indicates the scaling factor
to be used when interpreting the
value of the Data register. The
value and meaning of this field
will vary
DATA_SCALE field.
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
accessible. Sticky bit. These bits
are reset by POR. H_RESET,
S_RESET, or setting the STOP
bit has no effect.
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
tion does not support PME gener-
ation from D3cold.
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
cessible. Sticky bit. This bit is re-
set
S_RESET, or setting the STOP
bit has no effect.
are read only.
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
Data Scale. This 2-bit read-only
These bits are read only.
These bits are always read/write
PME
This bit defaults to “0” if the func-
If the function supports PME from
This bit is always read/write ac-
Reserved locations. These bits
00b - D0.
01b - D1.
10b - D2.
11b - D3.
by
Enable.
depending on the
POR.
When
H_RESET,
a
Am79C978
1,
PCI PMCSR Bridge Support Extensions Register
Offset 46h
Bit
7-0
PCI Data Register
Offset 47h
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to lower bytes of the
BCR37-BCR44 for testing purposes.
Bit
7-0
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C978 controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
PMCSR_BSE The PCI PMCSR Bridge Support
Name
Name
DATA_REG The PCI Data Register is an 8-bit
read, but their contents have no
effect on the operation of the de-
vice.
accessible.
Description
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. These bits are read
only.
Description
register. Refer to the “PCI Bus
Power Management Interface
Specification” version 1.0 for a
more detailed description of this
register.
at offset 47h in the PCI Configu-
ration Space. It is read only.
These bits can be written and
These bits are always read/write
The PCI PMCSR Bridge Support
The PCI DATA register is located
111