AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 144

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

Bit
31-4
3
2-0
CSR125: MAC Enhanced Configuration Control
Bit
31-16 RES
15-8
144
RES
RPA
RES
IPG
Name
Name
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times. The
decimal and hex values do not
Reserved locations. Written as
zeros and read as undefined.
Runt Packet Accept. This bit
forces the Am79C978 controller
to accept runt packets (packets
shorter than 64 bytes).
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Inter Packet Gap. Changing IPG
allows the user to program the
Am79C978 controller for aggres-
siveness on a network. By chang-
ing the default value of 96 bit
times (60h) the user can adjust
the fairness or aggressiveness of
the Am79C978 integrated MAC
on the network. By programming
a lower number of bit times other
then the ISO/IEC 8802-3 stan-
dard requires, the Am79C978
controller will become more ag-
gressive on the network. This ag-
gressive nature will give rise to
the Am79C978 controller possi-
bly “capturing the network” at
times by forcing other less ag-
gressive nodes to defer. By pro-
gramming a larger number of bit
times, the Am79C978 home net-
working MAC will become less
aggressive on the network and
may defer more often than nor-
mal. The performance of the
Am79C978 controller may de-
crease as the IPG value is in-
creased from the default value.
This bit is read accessible al-
ways; write accessible only when
STOP is set to 1. RPA is cleared
by H_RESET or S_RESET and is
not affected by STOP.
Description
Description
Am79C978
7-0
IFS1
match due to delays in the part
used to make up the final IPG.
Changes should be added or sub-
tracted from the provided hex val-
ue on a one-for-one basis.
CAUTION: Use this parameter
with care. By lowering the IPG
below the ISO/IEC 8802-3 stan-
dard
Am79C978 controller can inter-
rupt normal network behavior.
These bits are read accessible al-
ways. Write accessible when the
STOP bit is set to 1. IPG is set to
60h (96 Bit times) by H_RESET
or S_RESET and is not affected
by STOP.
InterFrameSpacingPart1. Chang-
ing IFS1 allows the user to pro-
gram the value of the InterFrame-
SpacePart1
Am79C978 controller sets the de-
fault value at 60 bit times (3ch).
See the subsection on Medium
Allocation in the section Media
Access Management for more
details. The equation for setting
IFS1 when IPG
IFS1 = IPG - 36 bit times
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times due
to the MII. The decimal and hex
values do not match due to de-
lays in the part used to make up
the final IPG.
Changes should be added or
subtracted from the provided hex
value on a one-for-one basis.
Due to changes in synchroniza-
tion delays internally through dif-
ferent network ports, the IFS1
can be off by as much as +12 bit
times.
These bits are read accessible al-
ways. Write accessible only when
the SPND bit or the STOP bit is
set to 1. IFS1 is set to 3ch (60 bit
times)
S_RESET and is not affected by
STOP.
96
by
bit
H_RESET
timing.
96 bit times is:
times,
The
the
or