AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 121

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

4
3
2
MPINT
MPINTE
MPEN
Am79C978 controller will only de-
tect a Magic Packet frame if the
destination address of the packet
matches the content of the physi-
cal address register (PADR). If
MPPLBA is set to 1, the destina-
tion address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the set-
ting of MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
gardless
destination address it has. This
bit is OR’ed with the EMPPLBA
bit (CSR116, bit 6).
cessible. MPPLBA is set to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Packet Interrupt is set by the
Am79C978 controller when the
device is in Magic Packet mode
and the Am79C978 controller re-
ceives a Magic Packet frame.
When MPINT is set to 1, INTA is
asserted if IENA (CSR0, bit 6)
and the enable bit MPINTE are
set to 1.
This bit is always read/write ac-
cessible. MPINT is cleared by the
host by writing a 1. Writing a 0
has no affect. MPINT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
This bit is always read/write ac-
cessible. MPINT is cleared to 0
by H_RESET or S_RESET and is
not affected by setting the STOP
bit.
lows activation of the Magic
Packet mode by the host. The
Am79C978 controller will enter
the Magic Packet mode when
This bit is always read/write ac-
Magic Packet Interrupt. Magic
Magic Packet Interrupt Enable. If
Magic Packet Enable. MPEN al-
of
what
kind
Am79C978
of
1
0
MPMODE
SPND
This bit is always read/write ac-
cessible. MPEN is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
This bit is always read/write ac-
cessible. MPMODE is cleared to
0 by H_RESET or S_RESET and
is not affected by setting the
STOP bit
Requesting entrance into the
suspend mode by the host de-
pends on the setting of the
FASTSPNDE bit (CSR7, bit 15).
Refer to the bit description of the
FASTSPNDE bit and the Sus-
pend section in Detailed Func-
tions, Buffer Management Unit
for details.
In suspend mode, all of the CSR
and BCR registers are accessi-
ble. As long as the Am79C978
controller is not reset while in
suspend mode (by H_RESET,
S_RESET, or by setting the
STOP bit), no re-initialization of
the device is required after the
device comes out of suspend
mode. The Am79C978 controller
will continue at the transmit and
receive descriptor ring locations
both MPEN and MPMODE are
set to 1.
ter the Magic Packet mode when
MPMODE is set to 1 and either
PG is asserted or MPEN is set to
1.
cause the Am79C978 controller
to start requesting entrance into
suspend mode. The host must
poll SPND until it reads back 1 to
determine that the Am79C978
controller has entered the sus-
pend mode. Setting SPND to 0
will get the Am79C978 controller
out of suspend mode. SPND can
only be set to 1 if STOP (CSR0,
bit 2) is set to 0. H_RESET,
S_RESET, or setting the STOP
bit will get the Am79C978 control-
ler out of suspend mode.
The Am79C978 controller will en-
Suspend. Setting SPND to 1 will
121